1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device that includes a transistor having a pillar structure and a method for manufacturing the same.
2. Description of Related Art
Recent semiconductor devices employ vertical transistors for higher integration. A vertical transistor includes a gate insulating film and a gate electrode which cover a side surface of a semiconductor pillar erected on a semiconductor substrate. Such components constitute a unit transistor having diffusion layers provided on both sides in a vertical direction of the semiconductor pillar. For example, Japanese Patent Application Laid-open No. 2011-23483 describes a vertical transistor that employs the structure that a gate electrode surrounds a composite pillar including a semiconductor pillar and an insulating pillar. Japanese Patent Application Laid-open No. 2009-81389 describes a step of removing a mask film from discrete pillars. The discrete pillars provides shielding from the surroundings.
In this type of conventional vertical transistor, when a contact plug that feeds power to a gate electrode is provided in a position that is overlapped with a diffusion layer provided under a semiconductor pillar in a plan view, if a displacement occurs, the contact plug reaches the diffusion layer and is then short-circuited. Accordingly, it is advantageous to provide the contact plug in a position that is overlapped with an element isolation region. Therefore, an insulating pillar provided in the element isolation region contacts the semiconductor pillar, and the gate electrode provided on a side surface of the semiconductor pillar is extended to the element isolation region.
The composite pillar formed by integrating the semiconductor pillar and the insulating pillar has the advantage that the contact plug that feeds power to the gate electrode can be located above a shallow trench isolation (STI), whereby a penetration short circuit to the semiconductor substrate can be avoided during the formation of the contact hole. The pillars are formed by using a mask film made of a silicon nitride film (SiN). The composite pillar makes it difficult to partly remove only the mask film on the semiconductor pillar, and the etchant can even spread over the mask film on the insulating pillar and unevenly etch the mask film. This makes it difficult to control the shape of the mask pattern.
The semiconductor pillar of the vertical transistor is formed to adjoin the insulating pillar which is a part of the element isolation region. The mask film used to form the pillars remains integrally on the upper surfaces of the respective pillars. Since the presence of the mask film can obstruct the formation of the diffusion layer in an upper portion of the semiconductor pillar, the mask film is removed by wet etching. The etching solution may sometimes flow out of the area of the semiconductor pillar and dissolve the mask film that is supposed to be left. The disappearance of the mask film can cause shape defects such as wiring disconnection and a short circuit in subsequent steps, with the problem of unstable operation of the vertical transistor.
FIG. 26 is a schematic plan view of a semiconductor device 300 before the removal of the mask film according to a related art. FIG. 27 is a schematic plan view of the semiconductor device 300 after the removal of the mask film according to the related art.
As shown in FIG. 26, an STI 2 serving as an element isolation region is provided on a silicon substrate 1 so as to surround an active region 1a. To form a silicon pillar (semiconductor pillar) 5, a mask film 4 made of a silicon nitride film is integrally arranged on the upper surfaces of the STI 2 and the silicon pillar 5. By using the mask film 4 as a mask, dry etching is performed to form two grooves 4A and 4B (hollow portions in the diagram). This also forms the silicon pillar 5 in the active region 1a between the grooves 4A and 4B. Insulating pillars 45, a part of the STI 2, are formed in the element isolation region between the grooves 4A and 4B.
As described above, the mask film 4 arranged on the upper surface of the silicon pillar 5 needs to be removed by wet etching. A mask film 13 made of a silicon dioxide film is arranged on the upper surface of the mask film 4 so that only the mask film 4 on the silicon pillar 5 is exposed through an opening 13a of the mask film 13. Such a nitride film removal step needs a high etching selectivity to the oxide film. Dry etching is not usable because it is difficult to etch the silicon nitride film with high selectivity to the silicon dioxide film. Wet etching capable of highly selective etching is thus used. Note that FIG. 26 shows the mask film 13 as a transparent film in order to clarify the arrangement of the underlying layers. The same applies to FIG. 27.
Next, turning to FIG. 27, the mask film 4 is selectively removed by wet etching, whereby the upper surface of the silicon pillar 5 is exposed. However, since an overetching condition is employed to completely remove the mask film 4 on the silicon pillar 5, the etchant laterally spreads out from the opening 13a of the mask film 13 to the STI 2 side as shown by the arrows, whereby a part of the mask film 4 covering the upper surfaces of the insulating pillars 45 is removed as well. The flow of the wet etching solution into the element isolation region covered by the mask film 13 causes the problem that the amount of the mask film 4 remaining on the upper surfaces of the insulating pillars 45 becomes unstable and the needed mask film 4 can also be removed.